1. Field of the Invention
The present invention relates to an electrostatic discharge protection circuit and a terminating resistor circuit. Particularly, the present invention relates to an electrostatic discharge protection circuit for protecting an internal circuit of a semiconductor device from electrostatic discharge. The invention also pertains to a terminating resistor circuit for stabilizing signals of a semiconductor device.
2. Description of the Related Art
An internal circuit of an LSI may be damaged by Electro Static Discharge (ESD) due to contact with a person and friction with a storage box. In order to protect the internal circuit from ESD, the LSI has an ESD protection circuit between a power supply terminal and a signal input/output terminal.
This ESD protection circuit has a capacitance due to transistors in the input stage for inputting voltage surge and causes RC delays or ZC delays in differential signals to be input/output to LSI terminals. Therefore, in the LSI which guarantees switching operations (pulse rise time: tr=500 ps to 1 ns) at several hundred MHz, the ESD protection circuit hinders the high-speed property of the internal circuit. Here, assume that a characteristic impedance (Z0) of a transmission line in the LSI inside is 100Ω and a capacitance (C) of the ESD protection circuit is 1 to 4 pF. In this case, a time constant at the LSI terminal is Z0C=100 to 400 ps and is just barely smaller than the pulse rise time tr so that a normal ESD protection circuit can still be used.
However, in LSIs (pulse rise time: tr=50 to 200 ps) improved in clock frequency and operating at several GHz, when a capacitance of the ESD protection circuit is 1 to 4 pF as described above, the time constant of the LSI terminal is larger than the pulse rise time.
As a result, an LSI slew rate during the switching is determined by the ESD protection circuit and reaches a peak with an operation at below 1 GHz.
In addition, there is conventionally proposed a semiconductor integrated circuit device for equalizing an ESD load imposed on each protection element within a protection circuit, and preventing the destruction of a transistor for protecting an internal circuit (see, e.g., Japanese Unexamined Patent Application Publication No. 2004-71991).
Thus, there is a problem that due to capacitance of the electrostatic discharge protection circuit, differential signals are delayed so that the speeding up of differential signals is difficult.
Also when a terminating resistor circuit is connected to a signal line through which differential signals propagate, there is a problem that due to parasitic capacitance of the terminating resistor circuit, differential signals are delayed so that speeding up of differential signals is difficult.